Time-interleaved Analog-to-Digital Converters (TIADC) have received considerable attention in the recent past in applications that require very high sample rates, i.e., sample rates that cannot be provided by a single ADC. In a TIADC system, a fast ADC is obtained by combining slower ADCs operating in parallel. Ideally, the slower ADCs should each have the same offset, the same gain, and the same uniform sample instants. In practice, however, due to fabrication errors, component mismatches, temperature variations, mechanical strain, environmental perturbations, etc., this requirement is difficult to achieve. The resulting errors degrade the performance of the TIADC system significantly, thus making the estimation and correction of these errors imperative to improve performance.